MTAAP 2014


Workshop on Multithreaded Architectures and Applications

May 23, 2014
Phoenix, Arizona USA


To be held in conjunction with the
28th IEEE International Parallel & Distributed Processing Symposium









Multithreading (MT) programming and execution models, as well as Many Integrated Core (MIC) and hybrid programming with accelerated architectures, are now part of the high-end and mainstream computing scene. This trend has been driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures and processors that fit this profile are Cray's XK and XMT, NVIDIA Kepler, Intel Phi, IBM Cyclops, and several SMT processors from IBM (Power7), AMD, or Intel, as well as heterogeneous clusters with accelerators from AMD and NVIDIA. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement.

The MTAAP 2014 workshop is a full-day meeting to be held at the IPDPS 2014 focusing on Multithreading Architectures and Applications. This workshop intends to identify applications that are amenable to MT, MIC, and hybrid programming and execution models, as well as the underlying architectures on which they can thrive. The workshop seeks to explore programming frameworks in the form of languages and libraries, compilers, analysis and debugging tools to increase the programmability. Topics of interest, of both theoretical and practical significance, include but are not limited to:


MTAAP 2014 Program - Friday, May 23, 2014


08:45 - 09:00 MTAAP 2014 Welcome

09:00 - 10:00 Algorithms & Position Papers

09:00: A New Parallel Algorithm for Two-Pass Connected Component Labeling

Siddharth Gupta (Northwestern University, USA); Diana Palsetia (Northwestern University, USA); Ankit Agrawal (Northwestern University, USA); Alok Choudhary (Northwestern University, USA)

09:30: Position Paper: Locality-Driven Scheduling of Tasks for Data-Dependent Multithreading

Jaime Arteaga (University of Delaware, USA); Stephane Zuckerman (University of Delaware, USA); Elkin Garcia (University of Delaware, USA); Guang Gao (University of Delaware, USA)

09:45: Position Paper: Leveraging Strength-Based Dynamic Slicing to Identify Control Reconvergence Instructions

Walid Ghandour (Lebanese University, Lebanon); Nadine Ghandour (Lebanese University, Lebanon)


10:00 - 10:30 Morning Break

10:30 - 12:00 Graph Analytics

10:30: Parallel Heuristics for Scalable Community Detection

Hao Lu (Washington State University, USA); Mahantesh Halappanavar (Pacific Northwest National Laboratory, USA); Ananth Kalyanaraman (Washington State University, USA); Sutanay Choudhury (Pacific Northwest National Laboratory, USA)

11:00: Hardware/Software Vectorization for Closeness Centrality on Multi-/Many-Core Architectures

Ahmet Erdem Sariyuce (The Ohio State University, USA); Erik Saule (University of North Carolina at Charlotte, USA); Kamer Kaya (The Ohio State University, USA); Umit V. Catalyurek (The Ohio State University, USA)

11:30: Revisiting Edge and Node Parallelism for Dynamic GPU Graph Analytics

Adam McLaughlin (Georgia Institute of Technology, USA); David A. Bader (Georgia Institute of Technology, USA)


12:00 - 13:30 Lunch

13:30 - 15:00 Accelerators

13:30: A Validation Testsuite for OpenACC 1.0

Cheng Wang (University of Houston, USA); Rengan Xu (University of Houston, USA); Sunita Chandrasekaran (University of Houston, USA); Barbara Chapman (University of Houston, USA); Oscar Hernandez (Oak Ridge National Laboratory, USA)

14:00: Extracting Maximal Exact Matches on GPU

Anas Abu-Doleh (The Ohio State University, USA); Kamer Kaya (The Ohio State University, USA); Mohamed Abouelhoda (Nile University, Lebanon); Umit V. Catalyurek (The Ohio State University, USA)

14:30: Predicting an Optimal Sparse Matrix Format for SpMV Computation on GPU

Bayyapu Neelima (National Institute of Technology-karnataka Surathkal, India); Ram Mohana Reddy Guddeti (NITK, Surathkal, India); Prakash Raghavendra (National Institute of Technology Karnataka Surathkal, India)  

15:00 Adjourn

Workshop Organization


Program Committee

Call for Papers

Paper Submission Guidelines

Submitted manuscripts should follow the IEEE conference style: not exceed 12 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Alternatively, authors can submit up to 15 single-spaced pages using 12-point size font on 8.5x11 inch pages, including figures, tables, and references. Authors may submit additional material as an appendix to their submission, but there is no guarantee that this material will influence the review process. Manuscripts must be submitted electronically and in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal.

Please click here for paper submission

Important Dates


The proceedings of this workshop will be published together with the proceedings of other IPDPS 2014 workshops by the IEEE Computer Society Press. Accepted papers will have a page limit of 10 pages, and authors can purchase an additional 2 pages, for a total of 12 pages maximum.

Workshop Archive

Information and papers from the earlier MTAAP workshops are available:

Additional Information

E-mail Contact

For more information on MTAAP or if you have any questions please contact the workshop chair at

Website URL

This website is hosted by the HPC Lab at Ohio State University.