MTAAP 2013


Workshop on Multithreaded Architectures and Applications

May 24, 2013
Boston, Massachusetts USA


To be held in conjunction with the
27th IEEE International Parallel & Distributed Processing Symposium








Paper Submission Deadline Extended to midnight of Jan 18, 2013


Multithreading (MT) programming and execution models, as well as Many Integrated Core (MIC) and hybrid programming with accelerated architectures, are now part of the high-end and mainstream computing scene. This trend has been driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures and processors that fit this profile are Cray's XK and XMT, NVIDIA Kepler, Intel Phi, IBM Cyclops, and several SMT processors from IBM (Power7), AMD, or Intel, as well as heterogeneous clusters with accelerators from AMD and NVIDIA. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement.

The MTAAP 2013 workshop is a full-day meeting to be held at the IPDPS 2013 focusing on Multithreading Architectures and Applications. This workshop intends to identify applications that are amenable to MT, MIC, and hybrid programming and execution models, as well as the underlying architectures on which they can thrive. The workshop seeks to explore programming frameworks in the form of languages and libraries, compilers, analysis and debugging tools to increase the programming productivity. Topics of interest, of both theoretical and practical significance, include but are not limited to:


MTAAP 2013 Program - Friday, May 24, 2013


08:15 - 08:30 MTAAP 2013 Welcome

08:30 - 10:00 Compiler and Tools

08:30: Capping Speculative Traces to Improve Performance in Simultaneous Multi-Threading CPUs

Yilin Zhang (The University of Texas at San Antonio) Wei-Ming Lin (The University of Texas at San Antonio)


09:00: CHiP: A Profiler to Measure the effect of Cache Contention on Scalability

Bevin Brett (Intel Corporation, USA); Pranith Kumar (Georgia Institute of Technology, USA); Minjang Kim (Georgia Institute of Technology, USA); Hyesoon Kim (Georgia Tech, USA)


09:30: Compiler-based Data Prefetching and Streaming Non-temporal Store Generation for Intel Xeon Phi Coprocessor

Rakesh Krishnaiyer (Intel Corporation, USA); Emre Kultursay (Pennsylvania State University, USA); Pankaj Chawla (Intel Corporation, USA); Serguei Preis (Intel Corporation, USA); Anatoly Zvezdin (Intel Corporation, USA); Hideki Saito (Intel Corporation, USA)


10:00 - 10:30 Morning Break

10:30 - 12:00 Scheduling and Runtime

10:30: The Pheet Task-Scheduling Framework on the Intel Xeon Phi and other Multicore Architectures

Martin Wimmer (Vienna University of Technology, Austria); Manuel Poter (Vienna University of Technology, Austria); Jesper Larsson Traff (Vienna University of Technology, Austria)


11:00: Toward a Scalable Heterogeneous Runtime System for the Convey MX Architecture

John Leidel (Convey Computer Corp., USA); Joe Bolding (Convey Computer Corp., USA); Geoffrey Rogers (Convey Computer Corp., USA)


11:30: Towards Memory-Load Balanced Fast Fourier Transformations in Fine-grain Execution Models

Chen Chen (University of Delaware, USA); Yao Wu (University of Delaware, USA); Stephane Zuckerman (University of Delaware, USA); Guang Gao (University of Delaware, USA)


12:00 - 13:30 Lunch

13:30 - 15:00 Graph Algorithms

13:30: Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search

Scott Beamer (University of California, Berkeley, USA); Aydin Buluc (Lawrence Berkeley National Laboratory, USA); Krste Asanovic (UC Berkeley, USA); David Patterson (UC Berkeley, USA)


14:00: Avoiding Locks and Atomic Instructions in Shared-Memory Parallel BFS Using Optimistic Parallelization

Rezaul A. Chowdhury (Stony Brook University, USA, USA); Jesmin Jahan Tithi (Stony Brook University, USA); Dhruv Matani (Stony Brook University, USA); Gaurav Menghani (Stony Brook University, USA)


14:30: Investigating Graph Algorithms in the BSP Model on the Cray XMT

David Ediger (Georgia Institute of Technology, USA); David A. Bader (Georgia Institute of Technology, USA)


15:00 - 15:30 Afternoon Break

15:30 - 16:30 Algorithms

15:30: Multithreaded Community Monitoring for Massive Streaming Graph Data

Jason Riedy (Georgia Institute of Technology, USA); David A. Bader (Georgia Institute of Technology, USA)


16:00: Scalable, Multithreaded, Partially-in-place Sorting

David J Haglin (Pacific Northwest National Laboratory, USA); Robert Adolf (Pacific Northwest National Laboratory, USA)


16:30 Adjourn

Workshop Organization


Program Committee

Call for Papers

Paper Submission Guidelines

Submitted manuscripts should follow the IEEE conference style: not exceed 12 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Alternatively, authors can submit up to 15 single-spaced pages using 12-point size font on 8.5x11 inch pages, including figures, tables, and references. Authors may submit additional material as an appendix to their submission, but there is no guarantee that this material will influence the review process. Manuscripts must be submitted electronically and in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal.

MTAAP Paper submission:

Important Dates


The proceedings of this workshop will be published together with the proceedings of other IPDPS 2013 workshops by the IEEE Computer Society Press. Accepted papers will have a page limit of 10 pages, and authors can purchase an additional 2 pages, for a total of 12 pages maximum.

Workshop Archive

Information and papers from the earlier MTAAP workshops are available:

Additional Information

E-mail Contact

For more information on MTAAP or if you have any questions please contact the workshop chair at

Website URL

This website is hosted by the HPC Lab at Ohio State University.