Ümit V. Çatalyürek

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ECE 662 - Theory and Design of Digital Computers, Spring 2011

Meeting Time:

3:30 pm MWF, McPherson Lab 1041

Instructor:

Prof. Umit V. Catalyurek

Office Hours:

4:30-5:30 pm MW @ 316DL (Other times are also available by appointment)

Textbook:

Computer Organization, 5th Edition by C. Hamacher, Z. Vranesic, and S. Zaky

Prerequisites:

ECE 265 or CSE 360, and ECE 561

Grading

Component

Contribution to Overall Grade

Homeworks

15%

Machine Problems

15%

Midterm Exams

40%

Final Exam

30%

General Comments

  1. For lecture notes and details of assignments visit http://carmen.osu.edu
  2. One week's notice will be given to announce the day of the midterm exam. No make-up exams will be given.
  3. Homeworks will be assigned most weeks. They will typically be due in one week. No late homeworks will be accepted.
  4. Grading questions must be resolved within one week of the time when the graded work is returned.
  5. Machine Problems include specifications for simple computers which are tested with a simulator program on the redhat workstations.
  6. Attendance is not compulsory but you are responsible for topics covered in class, announcements made in class, homework assigned in class, and submitting lab reports and special assignments on time. This web page will not be updated!
  7. As a common courtesy to the instructor and fellow students, please eliminate activity that is disruptive to the academic process during class, including but not limited to, use of cell phones, portable electronic music devices, handheld game consoles, and laptops (unless explicitly permitted); reading newspapers or magazines or solving crossword puzzles etc; chatting with class mates.

 

Topic

Lecture

Reading

Basic structure of computers

1

1-18

Motorola 68000 reg. structure, Simple Computer example

2

130-132

Bus structures, counter design

3

Appendix A

Number formats, arithmetic operations, overflow

4

25-32, 368-371

Memory locations, addresses

5

33-37

Instructions & instruction sequencing

6

37-47

Addressing modes

7

48-58, 131-136

68000 instruction set

8

94-98, 136-144, Appendix C

68000 stacks and subroutines

9

68-73, 146-151

Midterm 1

10

 

ECE662 simulator

11

 

OSIAC 662

12

411-425

OSIAC 662 - data paths

13

 

OSIAC 662 - general-purpose registers, adder

14

 

OSIAC 662 - open-collector bus, temporary regs.

15

 

Hardwired control

16

425-429

Example Control Unit

17

 

Encoder circuitry

18

 

Review for midterm

19

 

Midterm 2

20

 

Microprogrammed control

21

429-435

Memory basics

22

291-295, 313-314

Cache memories

23

314-322

Cache example

24

 

Cache mapping techniques

25

322-325

Machine problem

26

 

Direct memory access

27

234-237

Bus arbitration

28

237-240

Review for final

29

 

 

 

©2006 Umit Catalyurek. Last Update: Jan 18th, 2010